As AI workloads continue to surge, High Bandwidth Memory (HBM) has become a critical component in modern computing systems. However, conventional HBM architectures are approaching their physical limits, particularly in terms of stack height, I/O density, and thermal management. In response, Samsung is exploring a new architectural approach known as “Vertical Die” (V-die), which could redefine the future of advanced memory packaging.
According to ET News, Samsung’s V-die project, part of its Future Technology Research program, has made notable progress. The architecture is designed to deliver up to 10x higher I/O density and approximately 4x greater bandwidth compared to current HBM4 solutions.
Unlike traditional HBM, which stacks DRAM dies horizontally using through-silicon vias (TSVs), the V-die approach reorients chips vertically at a 90-degree angle. This design allows the entire edge of each die to function as a connection interface, significantly expanding the number of I/O channels without being constrained by TSV limitations. As a result, I/O counts could increase from around 2,048 in HBM4 to nearly 20,000 within the same footprint.
Beyond architectural innovation, the research also addresses key challenges in materials and signal integrity. The team has experimented with direct copper electroplating on glass substrates, widely considered a next-generation packaging material, while successfully maintaining signal integrity.
Thermal management, another major bottleneck in high-density chip stacking, is tackled through a novel “direct liquid cooling” approach. This method utilizes microscopic gaps between dies as channels for coolant flow, enabling more uniform and efficient heat dissipation across the entire structure.
The project, led by Professor Kwon Ji-min of KAIST, has reached a significant milestone with its research accepted for presentation at the IEEE Symposium on VLSI Technology and Circuits 2026, one of the most prestigious conferences in semiconductor technology.
Looking ahead, Vertical Die is not just an incremental improvement for HBM. It represents a potential platform for next-generation AI accelerators, high-performance computing (HPC), high-speed memory–logic integration, and advanced communication systems.
As the semiconductor industry races to meet the growing demands of AI, innovations at the architectural level like V-die could play a decisive role in shaping the next era of computing infrastructure.
