As HBM4 just begins mass production, Samsung is already moving ahead with its next-generation memory strategy. By targeting a 2nm base die for HBM5 and aggressively scaling HBM output, the company is positioning itself at the forefront of AI-driven computing.
Announced at NVIDIA GTC, Samsung plans to adopt a 2nm process for the base die of HBM5, replacing the 4nm node used in HBM4 and HBM4E. This transition is expected to significantly enhance both performance and power efficiency for future AI workloads.
In parallel, the upcoming HBM5E is set to integrate 1d DRAM as its core stacked memory. While this approach increases manufacturing costs, it is seen as necessary to meet the growing performance demands of advanced AI systems. Currently, HBM4 relies on 1c DRAM, while 1d DRAM is still under development and yet to be commercialized.
Beyond technology, Samsung is also scaling its production strategy. The company aims for HBM4 to account for more than 50% of its total HBM output, with overall HBM production expected to more than triple this year compared to last year.
Another notable development is Samsung’s expanding role within the ecosystem of NVIDIA. At its Pyeongtaek facility, Samsung is producing the inference-focused “Groq 3” chip, with mass production targeted between late Q3 and early Q4. The chip features a large die size exceeding 700 mm², resulting in significantly fewer chips per wafer, and utilizes a high proportion of SRAM to enable fast on-chip inference.
This move highlights Samsung’s strategic shift from being primarily a memory supplier to becoming a broader manufacturing partner in the AI value chain. As the competition in AI infrastructure intensifies, such vertical integration could play a critical role in strengthening its market position.
