Semiconductor companies are reportedly considering relaxing thickness standards for future HBM memory. The main reason is that upcoming generations such as HBM4E and HBM5 are expected to use stacks of up to 20 layers, making it increasingly difficult to maintain the thin profiles seen in earlier designs.
Currently, the thickness standard for HBM4 is about 775 micrometers. However, industry discussions suggest that the limit for future HBM generations could be raised to around 825-900 micrometers. If the threshold surpasses 900 micrometers, it would represent a much larger increase compared with previous generations.
20-Layer Stacking Makes Thin HBM Harder to Maintain
In earlier generations, the thickness of HBM was tightly controlled. Up to HBM3E, the standard remained around 720 micrometers. With HBM4, the limit was raised to 775 micrometers.
As manufacturers move toward 20-layer DRAM stacks, maintaining the same thickness becomes far more challenging from a technical standpoint. The more layers that are stacked together, the greater the overall height of the memory package, pushing the industry to reconsider current limits.
TSMC’s Advanced Packaging Technologies Also Influence the Shift
Another factor shaping these discussions is the emergence of next-generation packaging technologies. When system chips adopt TSMC’s SoIC technology, their thickness is expected to increase by several tens of micrometers compared with the current level.
This could make the overall package thicker, meaning HBM standards may also need to be adjusted accordingly. Major companies such as NVIDIA and Amazon Web Services are reportedly planning to adopt this packaging approach for future AI systems.
Relaxed Thickness Limits Could Slow Hybrid Bonding Adoption
Allowing thicker HBM could also impact the pace at which new bonding technologies are adopted, particularly hybrid bonding.
Today, DRAM dies in HBM are typically connected using TC bonding, which relies on heat and compression. Hybrid bonding, by contrast, directly connects copper interconnects between chips and wafers. This method removes the need for bumps between DRAM layers, allowing the spacing between dies to approach nearly zero and enabling thinner stacks.
However, hybrid bonding remains difficult to implement in mass production. It requires extremely clean surfaces, highly precise copper alignment, and manufacturing yields can drop significantly when bonding up to 20 stacked chips.
As a result, although major memory manufacturers continue investing in research and development, hybrid bonding has not yet been widely deployed in HBM manufacturing. Even Samsung, one of the companies most actively developing this technology, is expected to introduce it only partially, earliest in 16-layer HBM4E products.
